1. Field of Invention
The present invention relates to digital phase-locked loops (PLLs), and in particular, to phase-frequency detectors (PFD) used in delta sigma PLLs.
2. Description of the Related Art
Referring to FIG. 1, a conventional PFD 10 that has been used in many digital PLL designs (including delta sigma PLLs) includes two D-type flip-flops 12u, 12d, an AND gate 14 and a delay circuit 16, all interconnected substantially as shown. The flip-flops 12u, 12d are separately clocked by the reference signal R and feedback divisor signal N. With each rising edge of these input signals R, N, a logic one (VDD applied at the D-inputs) is clocked through to the output Q of each flip-flop 12U, 12D. The data output signals Q of the flip-flops 12U, 12D form the “pump up” UP and “pump down” DN signals used for controlling a charge pump circuit 20 in accordance with well known principles.
Whenever the reference signal R is asserted, the pump up signal UP is also asserted. Similarly, whenever the feedback signal N is asserted, the pump down signal DN is also asserted. When the pump up signal UP is asserted (and inverted by the inverter 18 within the charge pump 20), the output pull-up transistor P1 is turned on, thereby causing electrical charge to be sourced to, or “pumped” into, the output terminal 21. Conversely, when the pump down signal DN is asserted, the output pull down transistor N1 is turned on, thereby causing an electrical charge to be sunk from, or “pumped” out of, the output terminal 21. The logic AND gate 14 ensures that the data output signals Q of the flip-flops 12u, 12d are cleared following assertion of both signals UP, DN simultaneously. The delay circuit 16 (various types of which are well known in the art) delays the logical AND signal 15 so as to assert the clear, or reset, signal 17 at a predetermined point in time following simultaneous assertion of both signals UP, DN and thereby allow for proper signal set-up times and avoidance of signal race conditions, as well as ensure an adequate output pulse width to minimize crossover distortion (discussed in more detail below).
This type of PFD 10 is widely used due to the advantages afforded by its transfer function. As is well known, this type of PFD 10 has a transfer function such that the output signal 23 of the charge pump 20, due to the control signals UP, DN provided by the PFD 10, depends upon the phase difference between the two input signals R, N when the host PLL is in its phase-locked state, and depends upon the frequency difference between the input signals R, N when the host PLL is in its unlocked state. Accordingly, a digital PLL in which this PFD 10 is used will lock under any condition, in terms of the input signals R, N, regardless of the type of loop filter in use.
Referring to FIG. 2, most loop filters 22 have low pass frequency characteristics and typically consist of a serially-connected resistor R and capacitor C1 connected in shunt with another capacitor C2, as shown. In this type of second order loop filter, the series capacitor C1 generally has a larger capacitance value then the shunt capacitor C2.
Referring to FIG. 3, the transfer function, in terms of the filtered charge pump output signal/PFD_out/23a versus the input phase error θerr (i.e., the difference in phase between the two input signals R, N), can be represented as shown. Ideally, the gain of the PFD 10 is linear over the full range of −2π to +2π radians of phase error θerr including the region centered about zero phase error during which the host PLL is phase-locked. When the phase error θerr becomes greater then 2π radians, the output signal/PFD_out/23a begins to wrap and becomes proportional to the phase error θerr in a pattern that repeats every 2π radians. (This characteristic is that demonstrated by the average of the actual pump up UP and pump down DN control signals generated by the PFD circuit 10.)
Referring to FIG. 4, there are three basic conditions under which a PFD circuit, such as that 10 shown in FIG. 1 operates: during phase-lock, i.e., when the reference and feedback signal frequencies are equal; when the feedback signal frequency is greater then the reference signal frequency; and when the feedback signal frequency is less then the reference signal frequency. When the feedback and reference signal frequencies are equal (time interval T1), the reference R and feedback N signal pulses are in alignment, as are the pump up UP and pump down DN signals. As a result, the net output 23 from the charge pump 20 is zero. When the feedback signal frequency is greater than the reference signal frequency (time interval T2), the feedback signal N pulses lead those of the reference signal R, as do the signal pulses of the pump down signal DN as compared to the pump up signal UP. As a result, the net output 23 from the charge pump 20 is negative, i.e., a sinking of current, or charge, from the output terminal 21 (FIG. 1). Conversely, when the feedback signal frequency is less then the reference signal frequency (time interval T3), the reference signal R pulses lead those of the feedback signal N, as do the signal pulses of the pump up signal UP as compared to the pump down signal DN. As a result, the net output 23 of the charge pump 20 is positive, i.e., a sourcing of current, or charge, to the output terminal 21. (As should be understood, the foregoing discussion applies to a PLL in which the voltage controlled oscillator (VCO) 24 (FIG. 2) has a positive gain characteristic Kvco; for a VCO with a negative gain characteristic Kvco, the charge pump current pulses would be inverted.)
Referring to FIG. 5, as noted above, the transfer function of the PFD 10 is ideally linear through and about the region R centered at zero phase error, i.e., near and during phase-lock. As is well known in the art, phase detectors and PFDs are susceptible to crossover distortion (often referred to as a “dead zone”) within the region D of near-zero phase difference between the two input signals R, N. In this region D, the small signal gain is near zero and can have dramatic changes for very small input phase errors, thereby introducing frequency jitter in the output of the host PLL. When this small signal gain is so low, often approaching zero, the feedback loop is essentially broken and electrical charge will leak off the high impendence output node 21 of the charge pump 20 (FIG. 1) until the phase difference between the input signals R, N becomes sufficiently large for the phase detector to exit this dead zone D and turn the charge pump 20 back on to correct such phase error. (This happens as a result of the signal pulses of the reference R and feedback N signals becoming so close together near and at phase-lock that the PFD is unable to distinguish them.) As is also well known in the art, and as noted above, delay in the feedback circuit, e.g., via delay circuit 16 (FIG. 1), is introduced to ensure an adequate output pulse width to minimize the dead zone D. As shown in FIG. 5, once the dead zone D has been minimized, the linearity of the transfer function of the PFD 10 is limited by the mismatch between the pump up current (sourced by transistor P1 to the output terminal 21) and pump down current (sunk by transistor N1 from the output terminal 21) of the charge pump 20. The effect of such current mismatch is represented by the difference in the slopes of the transfer function of the PFD 10 in the regions above and below the horizontal axis. Mismatch between the charge pump currents (pump up and pump down) is a particularly significant problem for delta sigma PLLs due to problems associated with maintaining matched pump up and pump down currents provided by the charge pump 20 to the output terminal 21 (FIG. 1). Particularly with such currents typically being quite small, and with ever decreasing transistor dimensions, matching such small currents is virtually impossible, particularly over variations in operating conditions (e.g., power supply voltages and circuit operating temperature) and fabrication processes. As is well known, charge pump current mismatch is a significant problem for delta sigma PLLs because they intentionally introduce large phase errors (positive or negative) to the phase detectors (i.e., multiple VCO pulse periods of error), and it is important that the loop gain remain linear to avoid mixing the high energy, high frequency spurious offset signals down to lower frequencies where the loop filter can no longer adequately suppress them. Hence, the performance of a delta sigma PLL is often a function of how well the linearity of the combined PFD and charge pump circuitry can be maintained.
Accordingly, it would be desirable to have a PFD with substantially linear phase error gain within the phase error range centered about zero phase error, i.e., near and during phase-lock, without requiring precision matching of charge pump output currents.